Projects

RISC-V CPU

This project implements a RISC-V CPU, from behavior level (RTL) to tape-out.

Single Path Delay 32-Point FFT Processor

A 32-point pipelined Fast Fourier Transform processor. The design is based on radix2-DIF(decimation-in-frequency) algorithm with average SNR = 58.76.

Systolic Array for Smith-Waterman

Acceleration of Smith-Waterman, a dynamic programming algorithm for performing local sequence alignment. Reduce complexity from O(mn) to O(m+n).